1. Field of the Invention
The present invention relates to a semiconductor circuit, such as a data transmission circuit, etc. having an output circuit whose slew rate can be adjusted, a method for adjusting a slew rate of the semiconductor circuit, and an apparatus for automatically adjusting the slew rate of the output circuit.
2. Description of the Related Art
In a semiconductor circuit such as a data transmission circuit or the like, in order to achieve data transmission at high speed while decreasing data transmission cycles time, it is desired to increase the slew rate of an output signal from an output circuit forming an output stage of the data transmission circuit. If the slew rate is increased, the transmission waveform will not be satisfactory, due to an effect of frequency characteristics of a data transmission medium. Accordingly, in order to achieve both the high-speed data transmission and appropriately controlling of the transmission waveform, the data transmission circuit needs to be designed such that the slew rate of an output signal from its output circuit remains within a predetermined range of values.
Even if the data transmission circuit is thus designed, the slew rate of the output signal may not desirably be obtained, depending on the state of the manufactured output circuit or its usage period. In order to overcome this problem, there is disclosed a technique regarding an output buffer compensation circuit in Unexamined Japanese Patent Application KOKAI Publication No. H8-97693.
The disclosed circuit detects at least the current driving capacity of a semiconductor device included in an internal circuit P2, using a ring oscillator which is formed on a substrate P3 on which the semiconductor device is formed. In accordance with this resultant detection, a variable resistance value of a variable resistance element forming an output buffer is controlled so as to compensate for the slew rate of the semiconductor device. While compensating for the slew rate, a controlling signal generated using a counter or two D/A converters is used, and an MOS transistor is employed as a variable resistance element.
In the output buffer compensation circuit disclosed in the publication, the current driving capacity of the semiconductor device in the internal circuit P2 is detected using the ring oscillator. The detection of the current driving capacity of how much current can flow is detection of the resistance value according to Ohm's law, i.e., I=V/R. Accordingly, in the disclosed circuit, the slew rate compensation is performed by detecting the current driving capacity. In such a structure, if the same type of transistor as that included in the internal circuit or the ring oscillator is employed in the output buffer, it can be expected that slew rate compensation is achieved in the structure where the resistance of the transistor in the output buffer varies.
The slew rate can be obtained based on a time constant which is a product of a resistance value and parasitic capacitance in the output buffer. Thus, the accurate slew rate of the output buffer can not entirely be adjusted in a circuit having the structure where the parasitic capacitance has an effect. According to the disclosed technique, at least two D/A converters for generating a controlling signal for slew rate adjustment are necessary. In this structure, in order to maintain the accuracy of the D/A converters and to appropriately set a desired variable resistance value, the size of the compensation circuit is unwantedly increased and a complicated technique needs to be developed for manufacturing a compensation circuit.